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dxf2fig parses Autocad DXF input, then calls external routines to do either plotting or a fig conversion for xfig. The conversion is fairly complete. Layers (depths in xfig), blocks (compounds in xfig), colors, and linetypes are roughly preserved in the output file.

Electric is a sophisticated electrical CAD system that can handle many forms of circuit design, including: Custom IC layout (ASICs) Schematic drawing Hardware description language specifications Electro-mechanical hybrid layout (snip, this is an edited version of Electric's homepage) Electric handles these file formats: CIF I/O GDS I/O VHDL I/O DXF I/O PostScript, HPGL, and QuickDraw output For real functionality, one should consider installing support simulation software such as cad/spice.

FEAPpv is a general purpose finite element analysis program which is designed for research and educational use. The program is described in the references: The Finite Element Method, 6th ed., Vols. 1 and 2, by O.C. Zienkiewicz and R.L. Taylor, Elsevier, Oxford, 2005. FEAPpv is designed to be compatible for compilation in Unix/Linux and Windows PC environments. No support on use of the program will be provided.

Gerber Viewer (gerbv) is a viewer for Gerber files. Gerber files are generated from PCB CAD system and sent to PCB manufacturers as basis for the manufacturing process. The standard supported by gerbv is RS-274X. The basic difference between RS-274D (the old standard) and RS-274X is basically the addition of apertures in RS-274X. It might be possible to make an RS-274X file out of an RS-274D file and an aperture list. gerbv also supports drill files. The format supported are known under names as NC-drill or Excellon. The format is a bit undefined and different EDA-vendors implement it different. But basically you need to have the tools definition in the file, then the parser is quite tolerant. The different holes are shown as dots in the (scaled) correct size. The different layers of the PCB are separated into different files. gerbv can load all files at the same time and display them "on top of each other". You can independently turn them on and off.

GHDL is the leading VHSIC Hardware Description Language (VHDL) simulator. Digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits can be described by VHDL, and VHDL can also be used as a general purpose parallel programming language. GHDL compiles VHDL files and creates a binary which simulates the design. GHDL fully supports IEEE 1076-1987, IEEE 1-76-1993, IEEE 1076-2002 versions of VHDL, and partially IEEE 1076-2008.

Impact is an explicit Finite Element Program which simulates dynamic impact events. It has a range of elements, contact handling and different material laws. Models can be created and viewed with external programs or the included postprocessor.

Jspice3 is a circuit simulator developed to meet the needs of researchers working with superconducting Josephson junction circuits, yet the program has the flexibility and power to meet the needs of other technologies. Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added features. One added feature is a built-in graphical input front end for schematic capture. While displayed, simulations can be run and data plotted through this graphical interface. While not as powerful or as pretty as the Xic graphical interface, it holds its own in functionality. A significantly enhanced output plotting capability is provided, and Jspice3 has enhanced script interpretation capability.

GnuCap is the GNU Circuit Analysis Package. The primary component is a general purpose circuit simulator. It performs nonlinear dc and transient analyses, fourier analysis, and ac analysis. It is fully interactive and command driven. It can also be run in batch mode or as a server. Spice compatible models for the MOSFET (level 1-7) and diode are included in this release. GnuCap is not based on Spice, but some of the models have been derived from the Berkeley models. Unlike Spice, the engine is designed to do true mixed-mode simulation. Most of the code is in place for future support of event driven analog simulation, and true multi-rate simulation. If you are tired of Spice and want a second opinion, you want to play with the circuit and want a simulator that is interactive, you want to study the source code and want something easier to follow than Spice, or you are a researcher working on modeling and want automated model generation tools to make your job easier, try GnuCap.

GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog.

MeshDev is a mesh comparison software. It accepts two meshes as input and computes the geometrical deviation between the two meshes. It return numerical values and can optionaly generate visual results (with a pseudo-colored mesh corresponding to the measured deviation) in OpenInventor format.