Ports 搜索

Impact is an explicit Finite Element Program which simulates dynamic impact events. It has a range of elements, contact handling and different material laws. Models can be created and viewed with external programs or the included postprocessor.

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2000. The standard proper is due to be release towards the middle of the year 2000. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal.

Jspice3 is a circuit simulator developed to meet the needs of researchers working with superconducting Josephson junction circuits, yet the program has the flexibility and power to meet the needs of other technologies. Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added features. One added feature is a built-in graphical input front end for schematic capture. While displayed, simulations can be run and data plotted through this graphical interface. While not as powerful or as pretty as the Xic graphical interface, it holds its own in functionality. A significantly enhanced output plotting capability is provided, and Jspice3 has enhanced script interpretation capability.

Kicad is an open source (GPL) software for the creation of electronic schematic diagrams and printed circuit board artwork. Designed and written by Jean-Pierre Charras, a researcher at LIS (Laboratoire des Images et des Signaux) and a teacher in IUT de Saint Martin d'Heres (France), in the field of electrical engineering and image processing. Kicad is a set of four softwares and a project manager: * Eeschema: Schematic entry. * Pcbnew: Board editor. * Gerbview: GERBER viewer (photoplotter documents). * Cvpcb: footprint selector for components used in the circuit design. * Kicad: project manager.

A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, crossplatform compatible, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), DXF, CIF (Caltech Intermediate Form)

GnuCap is the GNU Circuit Analysis Package. The primary component is a general purpose circuit simulator. It performs nonlinear dc and transient analyses, fourier analysis, and ac analysis. It is fully interactive and command driven. It can also be run in batch mode or as a server. Spice compatible models for the MOSFET (level 1-7) and diode are included in this release. GnuCap is not based on Spice, but some of the models have been derived from the Berkeley models. Unlike Spice, the engine is designed to do true mixed-mode simulation. Most of the code is in place for future support of event driven analog simulation, and true multi-rate simulation. If you are tired of Spice and want a second opinion, you want to play with the circuit and want a simulator that is interactive, you want to study the source code and want something easier to follow than Spice, or you are a researcher working on modeling and want automated model generation tools to make your job easier, try GnuCap.

GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog.

LinuxCNC controls CNC machines. It can drive milling machines, lathes, 3d printers, laser cutters, plasma cutters, robot arms, hexapods, and more. - Accepts G-code input, drives CNC machines in response. - Active user community. - Several different GUIs available. - Compatible with many popular machine control hardware interfaces. - Supports rigid tapping, cutter compensation, and many other advanced control features. WARNING: This port is simulation-only for now.

MeshDev is a mesh comparison software. It accepts two meshes as input and computes the geometrical deviation between the two meshes. It return numerical values and can optionaly generate visual results (with a pseudo-colored mesh corresponding to the measured deviation) in OpenInventor format.

MeshLab is an open source, portable, and extensible system for the processing and editing of unstructured 3D triangular meshes. The system is aimed to help the processing of the typical not-so-small unstructured models arising in 3D scanning, providing a set of tools for editing, cleaning, healing, inspecting, rendering and converting this kind of meshes.