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Interface graphique de Code_Aster, en Tcl/Tk. Tcl/Tk interface to run Code_Aster (prepare and start calculations using run_aster). See the port french/aster.

atlc is a program designed for finding the properties (characteristic impedance, inductance per meter, capacitance per meter, velocity factor, electric field distribution) of any transmission line with 2 or 3 conductors (i.e. a normal line or coupler). It uses the finite difference method to determine these properties, and can handle any cross section. The program atlc needs to know shape of the transmission line's cross section. This cross section is stored in a data file, which happens to be a Windows bitmap file. The bitmap file is read by atlc, following which the program performs the analysis. Look in /usr/local/share/examples/atlc for some examples.

BasicDSP is an educational tool that makes it easy to experiment with simple Digital Signal Processing algorithms for audio signals. The input can either be taken from the sound card, or be a locally generated sine wave, white noise or impulse signal. The output is fed to the sound card, as well as to a virtual oscilloscope and spectrum analyzer.

NASTRAN-95 NASTRAN is the NASA Structural Analysis System, a finite element analysis (FEA) program completed in the early 1970's. It was the first of its kind and opened the door to computer-aided engineering. Subsections of a design can be modeled and then larger groupings of these elements can again be modeled. NASTRAN can handle elastic stability analysis, complex eigenvalues for vibration and dynamic stability analysis, dynamic response for transient and steady state loads, and random excitation, and static response to concentrated and distributed loads, thermal expansion, and enforced deformations. NOTE: There is no technical support available for this software.

Cascade is a program for analyzing the noise and distortion performance of a cascade of elements in an electronic system. A typical application of cascade is the analysis of a receiver. A text description of the receiver block diagram consisting of things like amplifiers, mixers, and filters is entered into cascade. Each element is characterized by its gain and optionally noise figure, and third order intercept point. The program then analyzes the system and produces a report detailing the performance at each stage. A summary is produced which shows the relative contributions to the total system performance of each block. This allows easy identification of what limits system performance.

ChipVault is a VHDL and Verilog Chip Design Organization tool which improves design efficiency by: - Providing the ability to Navigate and Edit files Hierarchically. - Automatically generating Schematic Component Port views of VHDL and Verilog RTL files. - Automating RTL instantiation and template generation. - Providing Revision Control (designed for HW, not SW development). - Supporting External Tool Hooks (bottom-up vcoms,etc). - Providing an Issue Tracking Log with sorting. - Providing Netlist sorting and hierarchy viewing. - Supporting web-sharing of RTL files (both encrypted and clear). - Fast and Nimble.

CIDER is a mixed-level circuit and device simulator. CIDER attempts to provide greater simulation accuracy than a stand-alone circuit or device simulator can provide. CIDER is based on the sequential mixed-level circuit and device simulator, CODECS. In common with CODECS, CIDER embeds the circuit simulator, SPICE3, which provides circuit simulation capabilities, analytical models for semiconductor devices, and an interactive user interface. An interface to the captive device simulator, DSIM, provides accurate, one- and two-dimensional numerical models based on the solution of Poisson's equation, and the electron and hole current- continuity equations. The input format of CIDER couples SPICE-like circuit descriptions to a device description format similar to the one used by the PISCES device simulator developed at Stanford University. As a result, CIDER should seem reasonably familiar to designers already accustomed to both these tools. SPICE is a general-purpose circuit simulation program for nonlinear DC, nonlinear transient, and linear AC analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, lossless and lossy transmission lines (two separate implementations), switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs.

The CuraEngine is a C++ console application for 3D printing GCode generation. It has been made as better and faster alternative to the old Skeinforge engine. The CuraEngine is pure C++ and uses Clipper from http://www.angusj.com/delphi/clipper.php. There are no external dependencies and Clipper is included in the source code without modifications. This is just a console application for GCode generation. For a full graphical application look at https://github.com/daid/Cura with is the graphical frontend for CuraEngine. The CuraEngine can be used separately or in other applications. Feel free to add it to your application. But to take note of the License.

Dinotrace is a signal waveform tracing tool that supports traces in the form of Verilog Value Change Dump (VCD), ASCII, Verilator, Tempest CCLI, COSMOS, Chango and Decsim Binary. Dinotrace is also equipped with an interface to GNU Emacs. Dinotrace was conceived in the early 1980's by Allen Gallotta at Digital Equipment Corporation, who wrote the code and supported it through version 4.2. When created, it was the first graphical display tool for the simulators being designed at Digital.

dxf2fig parses Autocad DXF input, then calls external routines to do either plotting or a fig conversion for xfig. The conversion is fairly complete. Layers (depths in xfig), blocks (compounds in xfig), colors, and linetypes are roughly preserved in the output file.