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TreeView X is program to display phylogenetic trees on Unix-like platforms. It can read and display NEXUS and Newick format tree files (such as those output by PAUP*, ClustalX, TREE-PUZZLE, and other programs). It has a subset of the functionality of the version of TreeView available for the Mac Classic and Windows (it is roughly equivalent to version 0.95 of TreeView).

"Wise2 is package that is focused on comparing DNA sequences at the level of its conceptual translation, regardless of sequencing error and introns. This really is a rewrite of the old wisetools package, which I wrote about 3 years ago. It can compare a single protein or a profile HMM to a genomic DNA sequence, and predict a gene structure. This is algorithm, called genewise, is one of the algorithms available in Wise2. There are other algorithms focused on EST data rather than genomic data, as well as some other algorithm curios." - from the web site (Ewan Birney)

ADMesh is a program for processing triangulated solid meshes. Currently, ADMesh only reads the STL file format that is used for rapid prototyping applications, although it can write STL, VRML, OFF, and DXF files. Features * Read and write binary and ASCII STL files * Check STL files for flaws (i.e. unconnected facets, bad normals) * Repair facets by connecting nearby facets that are within a given tolerance * Fill holes in the mesh by adding facets. * Repair normal directions (i.e. facets should be CCW) * Repair normal values (i.e. should be perpendicular to facet with length=1) * Remove degenerate facets (i.e. facets with 2 or more vertices equal) * Translate in x, y, and z directions * Rotate about the x, y, and z axes * Mirror about the xy, yz, and xz planes * Scale the part by a factor * Merge 2 STL files into one * Write an OFF file * Write a VRML file * Write a DXF file * Calculate the volume of a part

ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile C code for the API of spice simulators.

Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

atlc is a program designed for finding the properties (characteristic impedance, inductance per meter, capacitance per meter, velocity factor, electric field distribution) of any transmission line with 2 or 3 conductors (i.e. a normal line or coupler). It uses the finite difference method to determine these properties, and can handle any cross section. The program atlc needs to know shape of the transmission line's cross section. This cross section is stored in a data file, which happens to be a Windows bitmap file. The bitmap file is read by atlc, following which the program performs the analysis. Look in /usr/local/share/examples/atlc for some examples.

NASTRAN-95 NASTRAN is the NASA Structural Analysis System, a finite element analysis (FEA) program completed in the early 1970's. It was the first of its kind and opened the door to computer-aided engineering. Subsections of a design can be modeled and then larger groupings of these elements can again be modeled. NASTRAN can handle elastic stability analysis, complex eigenvalues for vibration and dynamic stability analysis, dynamic response for transient and steady state loads, and random excitation, and static response to concentrated and distributed loads, thermal expansion, and enforced deformations. NOTE: There is no technical support available for this software.

ChipVault is a VHDL and Verilog Chip Design Organization tool which improves design efficiency by: - Providing the ability to Navigate and Edit files Hierarchically. - Automatically generating Schematic Component Port views of VHDL and Verilog RTL files. - Automating RTL instantiation and template generation. - Providing Revision Control (designed for HW, not SW development). - Supporting External Tool Hooks (bottom-up vcoms,etc). - Providing an Issue Tracking Log with sorting. - Providing Netlist sorting and hierarchy viewing. - Supporting web-sharing of RTL files (both encrypted and clear). - Fast and Nimble.

CIDER is a mixed-level circuit and device simulator. CIDER attempts to provide greater simulation accuracy than a stand-alone circuit or device simulator can provide. CIDER is based on the sequential mixed-level circuit and device simulator, CODECS. In common with CODECS, CIDER embeds the circuit simulator, SPICE3, which provides circuit simulation capabilities, analytical models for semiconductor devices, and an interactive user interface. An interface to the captive device simulator, DSIM, provides accurate, one- and two-dimensional numerical models based on the solution of Poisson's equation, and the electron and hole current- continuity equations. The input format of CIDER couples SPICE-like circuit descriptions to a device description format similar to the one used by the PISCES device simulator developed at Stanford University. As a result, CIDER should seem reasonably familiar to designers already accustomed to both these tools. SPICE is a general-purpose circuit simulation program for nonlinear DC, nonlinear transient, and linear AC analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, lossless and lossy transmission lines (two separate implementations), switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs.

Dinotrace is a signal waveform tracing tool that supports traces in the form of Verilog Value Change Dump (VCD), ASCII, Verilator, Tempest CCLI, COSMOS, Chango and Decsim Binary. Dinotrace is also equipped with an interface to GNU Emacs. Dinotrace was conceived in the early 1980's by Allen Gallotta at Digital Equipment Corporation, who wrote the code and supported it through version 4.2. When created, it was the first graphical display tool for the simulators being designed at Digital.