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NETGEN is an automatic 3D tetrahedral mesh generator. It accepts input from constructive solid geometry (CSG) or boundary representation (BRep) from STL file format. The connection to a geometry kernel allows the handling of IGES and STEP files. NETGEN contains modules for mesh optimization and hierarchical mesh refinement.

Kicad is an open source (GPL) software for the creation of electronic schematic diagrams and printed circuit board artwork. Designed and written by Jean-Pierre Charras, a researcher at LIS (Laboratoire des Images et des Signaux) and a teacher in IUT de Saint Martin d'Heres (France), in the field of electrical engineering and image processing. Kicad is a set of four softwares and a project manager: * Eeschema: Schematic entry. * Pcbnew: Board editor. * Gerbview: GERBER viewer (photoplotter documents). * Cvpcb: footprint selector for components used in the circuit design. * Kicad: project manager.

PCB is an interactive printed circuit board editor for the X11 window system. PCB includes a rats nest feature, design rule checking, and can provide industry standard RS-274-X (Gerber), NC drill, and centroid data (X-Y data) output for use in the board fabrication and assembly process. PCB offers high end features such as an autorouter and trace optimizer which can tremendously reduce layout time.

KLayout is a viewer for GDS2 files.

Elmer - Open Source Finite Element Software for Multiphysical Problems. Elmer is an open source multiphysical simulation software mainly developed by CSC - IT Center for Science (CSC). Elmer development was started 1995 in collaboration with Finnish Universities, research institutes and industry. After it's open source publication in 2005, the use and development of Elmer has become international. Elmer includes physical models of fluid dynamics, structural mechanics, electromagnetics, heat transfer and acoustics, for example. These are described by partial differential equations which Elmer solves by the Finite Element Method (FEM).

This is GDS2, a module for quickly creating programs to read, write, and manipulate GDS2 (GDSII) stream files.

The EAGLE Layout Editor is an easy to use, yet powerful tool for designing printed circuit boards (PCBs). The name EAGLE is an acronym, which stands for Easily Applicable Graphical Layout Editor. The program consists of three main modules: o Layout Editor o Schematic Editor o Autorouter which are embedded in a single user interface. Therefore there is no need for converting netlists between schematics and layouts. This is a Light Freeware Edition. It has the following limitations: o The useable board area is limited to 100 x 80 mm (4 x 3.2 inches). o Only two signal layers can be used (Top and Bottom). o The schematic editor can only create one sheet. o Support is only available via email or through our forum (no fax or phone support). o Use is limited to non-profit applications or evaluation purposes. Apart from these limitations the EAGLE Light Edition can do anything the Professional Edition can do. You can even load, view and print drawings that exceed these limits!

Logisim is an educational tool for designing and simulating digital logic circuits. With its simple toolbar interface and simulation of circuits as you build them, it is simple enough to facilitate learning the most basic concepts related to logic circuits. With the capacity to build larger circuits from smaller subcircuits, and to draw bundles of wires with a single mouse drag, Logisim can be used (and is used) to design and simulate entire CPUs for educational purposes. Logisim is used by students at colleges and universities around the world in many types of classes, ranging from a brief unit on logic in general-education computer science surveys, to computer organization courses, to full-semester courses on computer architecture.

The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes.

Lcapy is an experimental Python package for teaching linear circuit analysis. It uses SymPy for symbolic mathematics. Lcapy can analyse circuits described with netlists using modified nodal analysis. Alternatively, Lcapy can analyse networks and circuits formed by combining one, two, and (some) three port networks.