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共有19,819项符合%22HTTP Server%22的查询结果,以下是第3,1913,200项(搜索用时0.007秒)
cad/brlcad-7.24.0 (Score: 0.0012383816)
CSG modelling system from the US Ballistic Research Laboratory
BRL-CAD is a powerful Combinatorial/Constructive Solid Geometry (CSG) solid modeling system that includes an interactive geometry editor, ray-tracing support for rendering and geometric analysis, network-distributed framebuffer support, image and signal-processing tools, and an embedded scripting language. The package is a collection of over 400 tools and utilities across over 750,000 lines of source code. Included is support for various geometric data format conversions, image and signal processing capabilities, sophisticated ray-tracing based lighting models, network distributed ray-tracing, massively parallel ray-tracing, animation capabilities, data compression, image handling, and interactive 3-D geometric editing. Included is an implementation of Weiler's n-Manifold Geometry (NMG) data structures for surface-based solid models and photon mapping.
cad/cascade-1.4 (Score: 0.0012383816)
Simple tool to analyze noise and distortion of a RF system
Cascade is a program for analyzing the noise and distortion performance of a cascade of elements in an electronic system. A typical application of cascade is the analysis of a receiver. A text description of the receiver block diagram consisting of things like amplifiers, mixers, and filters is entered into cascade. Each element is characterized by its gain and optionally noise figure, and third order intercept point. The program then analyzes the system and produces a report detailing the performance at each stage. A summary is produced which shows the relative contributions to the total system performance of each block. This allows easy identification of what limits system performance.
cad/chipvault-200607 (Score: 0.0012383816)
Project organizer for VHDL and Verilog RTL hardware designs
ChipVault is a VHDL and Verilog Chip Design Organization tool which improves design efficiency by: - Providing the ability to Navigate and Edit files Hierarchically. - Automatically generating Schematic Component Port views of VHDL and Verilog RTL files. - Automating RTL instantiation and template generation. - Providing Revision Control (designed for HW, not SW development). - Supporting External Tool Hooks (bottom-up vcoms,etc). - Providing an Issue Tracking Log with sorting. - Providing Netlist sorting and hierarchy viewing. - Supporting web-sharing of RTL files (both encrypted and clear). - Fast and Nimble.
cad/electric-9.06 (Score: 0.0012383816)
Sophisticated VLSI design system
Electric is a sophisticated electrical CAD system that can handle many forms of circuit design, including: - Custom IC layout (ASICs) - Schematic drawing - Hardware description language specifications For real functionality, one should consider installing support simulation software such as cad/spice.
cad/CalculiX-2.11 (Score: 0.0012383816)
Three-Dimensional Structural Finite Element Program
A Three-Dimensional Structural Finite Element Program CalculiX Finite Element Models can be build, calculated and post-processed. The pre- and post-processor is an interactive 3D-tool using the openGL API. Notice: The authors acknowledge that naming conventions and input style formats for CalculiX are based on those used by ABAQUS, a proprietary, general purpose finite element code developed and supported by Hibbitt, Karlsson & Sorensen, Inc (HKS) and are used with kind permission from HKS. Results obtained from CalculiX are in no way connected to ABAQUS. note: By default the single-threaded solver is used, this can be changed by setting the OMP_NUM_THREADS environment variable with the number of processors you want to use.
cad/fritzing-0.9.2 (Score: 0.0012383816)
CAD for printed circuit boards
Fritzing is an Electronic Design Automation software with a low entry barrier, suited for the needs of designers and artists. It uses the metaphor of the breadboard, so that it is easy to transfer your hardware sketch to the software. From there it is possible to create PCB layouts for turning it into a robust PCB yourself or by help of a manufacturer.
cad/geda-1.8.2 (Score: 0.0012383816)
GPL Electronic Design Automation tools
The GPL Electronic Design Automation (gEDA) project has produced and continues working on a full GPL'd suite and toolkit of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production. Currently, the gEDA project offers a mature suite of free software applications for electronics design, including schematic capture, attribute management, bill of materials (BOM) generation, netlisting into over 20 netlist formats, analog and digital simulation, and printed circuit board (PCB) layout. The gEDA/gaf suite provides schematic capture, netlisting, bill of materials generation, and many other features.
cad/FreeCAD-0.17.g20160907 (Score: 0.0012383816)
General purpose 3D CAD modeller
FreeCAD is a general purpose parametric 3D modeler. FreeCAD is aimed directly at mechanical engineering and product design but also fits in a wider range of uses around engineering, such as architecture or other engineering specialties. FreeCAD features tools similar to Catia, SolidWorks or Solid Edge, and therefore also falls into the category of MCAD, PLM, CAx and CAE. It is a feature based parametric modeler with a modular software architecture which makes it easy to provide additional functionality without modifying the core system. FreeCAD is under heavy development and might not be ready for production use.
cad/gtkwave-3.3.76 (Score: 0.0012383816)
Electronic Waveform Viewer
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
cad/iverilog-10.1.1 (Score: 0.0012383816)
Verilog simulation and synthesis tool
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2000. The standard proper is due to be release towards the middle of the year 2000. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal.