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gSpiceUI is intended to provide a GUI for freely available electronic circuit simulation engines ie. NG-Spice and GNU-Cap. The utility gnetlist is used to convert schematic files to netlist files, Gwave or Gaw to display simulation results and gschem is the preferred schematic capture tool.

IRSIM is an event-driven logic-level simulator for MOS circuits. To run irsim, users should set CAD_HOME to the base installation directory where magic was installed, e.g. /usr/local. Alternatively, the system administrator can create a dummy user named 'cad' with its home directory set to the installation directory.

Magic is an interactive editor for VLSI layouts that runs under BSD. To run magic, users should set CAD_HOME to the base installation directory where magic was installed, e.g. /usr/local. Alternatively, the system administrator can create a dummy user named 'cad' with its home directory set to the installation directory.

MeshLab is an open source, portable, and extensible system for the processing and editing of unstructured 3D triangular meshes. The system is aimed to help the processing of the typical not-so-small unstructured models arising in 3D scanning, providing a set of tools for editing, cleaning, healing, inspecting, rendering and converting this kind of meshes.

NETGEN is an automatic 3D tetrahedral mesh generator. It accepts input from constructive solid geometry (CSG) or boundary representation (BRep) from STL file format. The connection to a geometry kernel allows the handling of IGES and STEP files. NETGEN contains modules for mesh optimization and hierarchical mesh refinement.

The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes.

Verilog-mode.el is a Verilog mode for Emacs which provides context-sensitive highlighting, auto indenting, and provides macro expansion capabilities to greatly reduce Verilog coding time. Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand Verilog-2001 ".*" instantiations, to see what ports will be connected by simulators.

CElvis 是 vi/ex 的克隆版本，一个标准的 UNIX 下的编辑器。CElvis 支持 几乎所有的 vi/ex 命令，无论是可视化模式还是冒号模式。 它也允许显示和编辑使用中文 GB（简体）和Big-5（繁体）编码的文档。 Celvis 基于 Elvis version 1.3， 由 Steve Kirkendall 开发。 David O'Brien obrien@cs.ucdavis.edu

你是不是有 X Windows 不认识的 TrueType 字体？可能是因为这个字体使用的编码不 是 Unicde！Open Type Organizer (oTo) 可以显示你的字体信息并通过翻译原始的 字体来添加新的“name”和“cmap”表。

这个 port 安装 4 个中文 Big5/GB TrueType 字体，包含楷体/明体（Big5）和楷体/宋体（GB）。 它可以在 X 窗口系统或类似 CJK 的排版软件中使用。感谢 Arphic 技术， 你可以在基于 GPL 的协议下自由地分发这些高质量的字体。详见 ARPHIC_*.TXT。