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tRNAscan-SE was written in the PERL (version 5.0) script language. Input consists of DNA or RNA sequences in FASTA format. tRNA predictions are output in standard tabular or ACeDB format. tRNAscan-SE does no tRNA detection itself, but instead combines the strengths of three independent tRNA prediction programs by negotiating the flow of information between them, performing a limited amount of post-processing, and outputting the results in one of several formats.

Trimmomatic performs a variety of useful trimming tasks for illumina NGS paired-end and single ended data.

"Wise2 is package that is focused on comparing DNA sequences at the level of its conceptual translation, regardless of sequencing error and introns. This really is a rewrite of the old wisetools package, which I wrote about 3 years ago. It can compare a single protein or a profile HMM to a genomic DNA sequence, and predict a gene structure. This is algorithm, called genewise, is one of the algorithms available in Wise2. There are other algorithms focused on EST data rather than genomic data, as well as some other algorithm curios." - from the web site (Ewan Birney)

Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

CIDER is a mixed-level circuit and device simulator. CIDER attempts to provide greater simulation accuracy than a stand-alone circuit or device simulator can provide. CIDER is based on the sequential mixed-level circuit and device simulator, CODECS. In common with CODECS, CIDER embeds the circuit simulator, SPICE3, which provides circuit simulation capabilities, analytical models for semiconductor devices, and an interactive user interface. An interface to the captive device simulator, DSIM, provides accurate, one- and two-dimensional numerical models based on the solution of Poisson's equation, and the electron and hole current- continuity equations. The input format of CIDER couples SPICE-like circuit descriptions to a device description format similar to the one used by the PISCES device simulator developed at Stanford University. As a result, CIDER should seem reasonably familiar to designers already accustomed to both these tools. SPICE is a general-purpose circuit simulation program for nonlinear DC, nonlinear transient, and linear AC analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, lossless and lossy transmission lines (two separate implementations), switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs.

Dinotrace is a signal waveform tracing tool that supports traces in the form of Verilog Value Change Dump (VCD), ASCII, Verilator, Tempest CCLI, COSMOS, Chango and Decsim Binary. Dinotrace is also equipped with an interface to GNU Emacs. Dinotrace was conceived in the early 1980's by Allen Gallotta at Digital Equipment Corporation, who wrote the code and supported it through version 4.2. When created, it was the first graphical display tool for the simulators being designed at Digital.

FidoCadJ is an easy to use graphical editor, with a library of electrical symbols and footprints (traditional and SMD). It aims to be an agile and effective small EDA tool for hobbyists. FidoCadJ stores its drawings in a compact text format, practical for the copy and paste in newsgroups and forums: this has determined its success on the Usenet and in numerous communities.

Jspice3 is a circuit simulator developed to meet the needs of researchers working with superconducting Josephson junction circuits, yet the program has the flexibility and power to meet the needs of other technologies. Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added features. One added feature is a built-in graphical input front end for schematic capture. While displayed, simulations can be run and data plotted through this graphical interface. While not as powerful or as pretty as the Xic graphical interface, it holds its own in functionality. A significantly enhanced output plotting capability is provided, and Jspice3 has enhanced script interpretation capability.

A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, crossplatform compatible, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), DXF, CIF (Caltech Intermediate Form)

NETGEN is an automatic 3D tetrahedral mesh generator. It accepts input from constructive solid geometry (CSG) or boundary representation (BRep) from STL file format. The connection to a geometry kernel allows the handling of IGES and STEP files. NETGEN contains modules for mesh optimization and hierarchical mesh refinement.